1. Technical Field of the Invention
The present invention relates to low to high voltage level translators. A low to high voltage level translator allows for the conversion of a digital input signal between ground and a low voltage, for example, 1.2 V, to a digital input signal between ground and a high voltage, for example, 3.3 V.
There are many known applications of voltage level translators. Voltage level translators may, for example, be used in memories, in input/output circuits (I/O circuits), or in analog circuits, (power management circuits, charge pumps, and the like). A voltage level translator may be used in any circuit operating with a dual voltage.
2. Description of Related Art
FIG. 1 illustrates an example of low to high voltage level translator according to the Prior Art.
The low to high level translator 10 comprises a first stage 1 and a second stage 2, connected in series between a ground voltage and a high power supply voltage VDDH.
The second stage 2 is connected to ground. The second stage 2 comprises a first nMOS transistor 4 and a second nMOS transistor 3, arranged to force to the ground voltage a first connection node 9 and a second connection node 8, respectively.
A digital output signal OUT is read at the first connection node 9. The second stage 2 is arranged to force the digital output signal OUT to the ground voltage.
The first nMOS transistor 4 is driven by a voltage at a first control node 14 and the second nMOS transistor 3 is driven by a voltage at a second control node 13. The voltages at said first and second control nodes are controlled by complementary control signals Vc1, Vc2 derived from a digital input signal IN to be translated.
The first stage 1 is arranged to force the digital output signal OUT to a high power supply voltage VDDH. The first stage 1 is connected to the high power supply voltage VDDH. The first stage 1 comprises a first pMOS transistor 6 and a second pMOS transistor 5, respectively arranged to force to the high power supply voltage VDDH the first connection node 9 and the second connection node 8. The first pMOS transistor 6 is driven by the voltage at the second connection node 8 and the second pMOS transistor 5 is driven by the voltage at the first connection node 9.
An inverter 7 may allow to provide the second control signal Vc2 from the digital input signal IN. The first control signal Vc1 may equal the digital input signal IN.
When the digital input signal IN has a value corresponding to a ‘0’, i.e. the voltage of the digital input signal IN substantially equals the ground voltage, the first NMOS transistor 4 is driven by a value corresponding to a ‘1’. The first nMOS transistor 4 is subsequently on, thus forcing the digital output signal OUT to the ground voltage.
The second pMOS transistor 5 driven by the voltage of the digital output signal OUT is hence on, thus forcing the second connection node 8 to the high power supply voltage VDDH.
The first pMOS transistor 6 driven by the voltage at the second connection node 8 is hence off, thus avoiding a current between the high power supply voltage VDDH and the digital output signal OUT. Furthermore, the voltage difference between the source terminal of the second NMOS transistor 3 and its gate terminal equals substantially zero. The second nMOS transistor 3 is hence blocked, thus avoiding a current between the second connection node 8 and the ground.
When the digital input signal IN has a value corresponding to a ‘1’, i.e. the voltage of the digital input signal IN substantially equals the low power supply voltage, the second nMOS transistor 3 is on, thus forcing the second connection node 8 to the ground voltage. The first pMOS transistor 6 driven by the second connection node 8 is subsequently on, thus forcing the digital output signal OUT to the high power supply voltage VDDH.
The second pMOS transistor 5 driven by the voltage of the digital output signal OUT is hence off, thus avoiding a current between the high power supply voltage VDDH and the second connection node 8.
Furthermore, as the digital input signal IN has a value corresponding to a ‘1’, the second control signal Vc2 has a value corresponding to a ‘0’. The first NMOS transistor is hence blocked, thus avoiding a current between the first connection node 9 and the ground.
The transistors 3, 4, 5, 6 have to support voltages between ground and the high power supply voltage at their source terminals and drain terminals. Therefore, the transistors 3, 4, 5, 6 are designed for use with relatively high voltages. The transistors 3, 4, 5, 6 may be, for example, double oxide CMOS transistors.
Double oxide CMOS transistors are designed to operate within a voltage range varying from the ground voltage to the high power supply voltage.
However, the first nMOS transistor 3 and the second nMOS transistor 4, although being double oxide transistors, are driven by relatively low voltages, i.e. a signal varying between the ground voltage to the low power supply voltage.
Advances in semiconductor fabrication and manufacturing lead to decreasingly low power supply voltage values, e.g. 1V or even less than 1V.
When driven by a power supply voltage having such a relatively low value, e.g. 0.9V, a double oxide transistor designed to be driven by a relatively high power supply voltage, e.g. 3.3 V, may exhibit relatively poor performances. Typically, relatively long transition times may prevent the double oxide transistor to operate properly with relatively high frequencies.
There is accordingly a need to provide a voltage level translator with better performance, even when driven by a digital input signal taking on relatively low values.